rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad9561 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 world wide web site: http://www.analog.com fax: 617/326-8703 ? analog devices, inc., 1996 pulse width modulator functional block diagram ramp ramp clock r set cal in 8-bit data sem/dem lem/tem retrace ref dac output logic pwm out cal dac internal timing l a t c h l a t c h ad9561 cal out cal out features 60 mhz pulse rate 8-bit resolution center, left or right justify low power: 700 mw typical minimum pulse width: <5 ns maximum pw: 100 % full-scale applications laser printers digital copiers color copiers general description the ad9561 is a second generation high speed, digitally programmable pulse width modulator (pwm). output pulse width is proportional to an 8-bit data input value. two additional control inputs determine if the pulse is placed at the beginning, middle or end of the clock period. pulse width and placement can be changed every clock cycle up to 60 mhz. pulse width modulation is a well proven method for controlling gray scale and resolution enhancement in scanning laser print engines. modulating pulse width provides the most cost effective method for continuous tone reproduction and resolu- tion enhancement in low-to-moderate cost scanning electro- photographic systems. the ad9561 uses precision analog circuits to control dot size so that near-photographic quality images are practical without the high frequ ency clock signals required by all digital approaches. the ad9561 has improved features and performance over its predecessor, the ad9560. an improved ramp topology enables control of pulse width through 100% of the dot clock period as opposed to 95% for the ad9560. this enables smooth transi- tion across dot boundaries for line screen applications. additionally, input data setup and hold time are symmetrical at 2 ns each, simplifying interface to the system bus. finally, chip design and pinout are optimized to decrease sensitivity of analog circuits to digital coupling. (see layout section for detailed recommendations for optimum results.) inputs are ttl or cmos compatible, and outputs are cmos compatible. the ad9561jr is packaged in a 28-lead plastic soic. it is rated over the commercial temperature range, 0 c to +70 c. highlights 1. 60 mhz native printer clock rate. 2. single +5 v power supply. 3. on-chip autocalibration. 4. pulse placement flexibility. 5. high resolution: 256 pulse widths.
C2C rev. 0 ad9561Cspecifications (+v s = +5 v; r set = 715 v , clock = 20 mhz unless otherwise noted) ad9561jr parameter temp min typ max units resolution 8 bits accuracy (@ 20 mhz) differential nonlinearity +25 c 0.5 2 lsb integral linearity 1 +25 c 1.5 4 lsb odd/even pulse mismatch 2 +25 c 0.75 lsb digital inputs logic 1 voltage full 2.0 v logic 0 voltage full 0.8 v input current full 1 m a input capacitance +25 c 5pf data setup time full 2.0 0.3 ns data hold time full 2.0 0.3 ns minimum clock pulse width (high) full 6 ns dynamic performance maximum trigger rate full 60 mhz minimum propagation delay (t pd ) 3 +25 c122028ns minimum propagation delay tc full 60 ps/ c output pulse width @ code 25 4 full 5 ns output pulse width @ code 255 full 100 % clock output rise time 5, 6 full 1.8 3 ns output fall time 5, 6 full 1.8 3 ns retrace propagation delay full 6 ns pwm output logic 1 voltage 5, 6 full 4.6 v logic 0 voltage 5, 6 full 0.4 v cal out logic 1 voltage full 4.6 v logic 0 voltage full 0.4 v power supply 7 positive supply current (+5.0 v) full 140 170 ma power dissipation full 700 850 mw power reduce current full 70 85 ma power reduce dissipation full 350 425 mw power supply rejection ratio propagation delay sensitivity (tem) 8 +25 c 1.5 ns/v notes 1 best fit between codes 25 and 230. inl is very layout sensitive. 2 due to linearity mismatch in dual ramps. 3 measured from rising edge of clock to transition of codes 0 to 255. 4 minimum pulse width (at 20 mhz) limited by rise time. pulse width for code 25 will be greater when clock < 20 mhz. 5 output load = 10 pf and 2 ma source/sink. 6 load conditions to test output drive capability. linearity will degrade with either capacitive or current loading. best linearity obtained driving a single cmos input. 7 all performance specifications valid when supply maintained at +5 v, 5%. 8 tested from +4.75 v to +5.25 v. specification subject to change without notice.
ad9561 C3C rev. 0 absolute maximum ratings 1 positive supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . +7 v digital input voltage range . . . . . . . . . . . . . . . C0.5 v to v dd minimum r set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 w digital output current (sourcing) 2 . . . . . . . . . . . . . . . 10 ma digital output current (sinking) 2 . . . . . . . . . . . . . . . . 10 ma operating temperature range 3 . . . . . . . . . . . . . 0 c to +70 c storage temperature range . . . . . . . . . . . . C65 c to +150 c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150 c lead soldering temperature (10 sec) 4 . . . . . . . . . . . . +300 c notes 1 absolute maximum ratings are limiting values, to be applied individually, and beyond which serviceability may be impaired. functional operation under any of these conditions is not necessarily implied. 2 cal out should drive a single ttl or cmos input. 3 typical thermal impedance: 28-lead soic (plastic) q ja = 71.4 c/w; q jc = 23 c/w. 4 when soldering surface mount packages in vapor phase equipment, temperature should not exceed 220 c for more than one minute. ordering guide temperature package package model range description option ad9561jr 0 c to +70 c 28-lead soic r-28 AD9561JR-REEL* 0 c to +70 c 28-lead soic r-28 *tape and reel ordered in multiples of 1000 ics. pin configuration 28 27 26 22 21 20 19 18 17 25 24 23 top view (not to scale) 1 2 3 7 8 9 10 11 12 4 5 6 13 14 16 15 ad9561 out v dd d2 d1 gnd v dd retrace cal start v dd gnd d0 (lsb) lem/tem sem/dem gnd d3 d4 d5 v dd gnd v dd cal out gnd d7(msb) clock gnd r set d6 pwr reduce pin descriptions pin name description 1C5 d3Cd7 digital data bits, d7 is msb 6 clock clock input 7v dd +5 v supply 8 gnd ground return 9v dd +5 v supply 10 gnd ground return 11 cal out calibration complete output 12 power reduce place ad9561 in sleep mode 13 gnd ground return 14 r set ramp current set resistor 15 gnd ground return 16 v dd +5 v supply 17 cal start initiates calibration cycle 18 retrace force output high 19 v dd +5 v supply 20 gnd ground return 21 out modulated pulse out 22 gnd ground return 23 v dd +5 v supply 24 lem/tem controls leading (1) or trailing (0) edge modulation 25 sem/dem controls single (1) or dual (0) edge modulation 26C28 d0Cd2 digital data bits, d0 is lsb warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad9561 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ad9561 C4C rev. 0 theory of operation general the ad9561 is a mixed signal ic designed to provide high- speed pulse width modulation in laser printers and copiers. it uses high performance analog circuits to achieve high resolution pulse control without requiring the excessively high clock rates of an all digital solution. because of the sensitivity of analog circuits to digital crosstalk, pcb layout is critical for achieving optimum results. please read the layout section at the end of this data sheet and follow suggestions completely for best performance. the ad9561 was designed to facilitate either higher effective resolution or photo-realistic image reproduction on low cost laser print platforms. its 8-bit pulse width resolution and pulse positioning capabilities combine to offer the highest level of gray shading and resolution enhancement flexibility available. it also in cludes an autocalibration circuit to minimize external components, and eliminates an extra burden on the system microprocessor. the functional block d iagram illustrates the analog content, comp rising ramp generators, dacs and comparators that generate a series of pulses. these pulses are combined in the output logic to form pwm out pulses whose width is propor- tional to the 8-bit data and whose position is determined by the sem/dem and lem/tem inputs. the ad9561 employs a proprietary ramp topology that eliminates the loss of dynamic range at the ends of the ramp. the functional block diagram is shown for illustration purposes only and does not represent the actual implementation. modulation modes positioning the width controlled pulses at the beginning, middle or end of the clock period, as shown in figure 2, adds significantly to the flexibility of the ad9561. this is accom- plished through control bit sem/dem and lem/tem. these acronyms represent single-edge modulation/dual-edge modulation and leading-edge modulation/trailing-edge modulation. sem/dem and lem/tem are collectively identified as control. leading edge modulation trailing edge modulation dual edge modulation figure 2. modulation modes pulse positioning within the clock period is defined by the following table: table i. truth table sem/dem lem/tem alignment 1 1 lem 1 0 tem 0 x dem single-edge modulation offers two options in which one edge is modulated while the other remains fixed relative to the clock. for leading-edge modulation, the rising edge of the pulse is delayed from the leading edge of the clock proportional to data, and the falling edge remains fixed at the end of the clock period. this may also be called right-hand justified. similarly, trailing-edge modulation has the rising edge fixed on the beginning of the clock period and the falling edge delayed proportional to data. this can be called left-hand justified. dual-edge modulation is often called center justified because the delay of both edges varies relative to the clock. with increasing values for data, pulse width increases with its center remaining constant proportional to the clock. like data, modulation control inputs sem/dem, and lem/tem can be updated at the clock rate up to 60 mhz. figure 1. pulse pattern example n+1 n+1 pulse n pulse n+1 clock data control output n ff, xx 100% dnc 0% dnc 75% tem 75% dem 87% lem 75% dem 75% dem 50% dem 25% dem 0% dnc 00, xx c0, 10 c0, 0x c0, 0x 80, 0x 40, 0x 00, xx c0, 0x e0, 11 ff, xx
ad9561 C5C rev. 0 pulse pattern example figure 1 at the top of the previous page illustrates the pwm out of the ad9561 with various data and control inputs. the data format is binary. in the pulse pattern example, the hexadecimal format is used, i.e., ff h represents decimal 255. the top line shows the clock; the second shows data and control inputs, which are latched on the rising edge of clock. the third line shows the resulting pulse. the ad9561 data and control inputs are double latched. the output pulse labeled pulse n results from data and control values latched in by the first clock, illustrating the one clock period timing delay. the control value number for pulse one is shown as xx. this means the value is not important because a 100% pulse will be output for any control value for data value 255 or ff h . likewise, output pulse n is noted as 100% dnc (do not care), also noting that control value is unimportant. the fourth data/control value is c0/0x. this indicates that the level for lem/tem is unimportant when sem/dem is logic level 0. selecting r set because the ad9561 must provide full range coverage of the clock pulse period, the ramp time must be matched to the clock period. all components for the ramp generators, except r set , are integrated in the ad9561. r set , is selected by the user to set the ramp time close to the clock period. the ramps are generated by constant current sources charging on-chip capacitors. r set can be chosen in the range from 226 w for 60 mhz operation to 16.5 k w for 1 mhz. because the absolute value of the on-chip capacitor can vary by 20%, the autocalibration circuit is included to fine tune the matching of the ramp time to the clock period. r set ?k w 100 10 1 020 1 clock frequency ?mhz 10 figure 3. r set values vs. clock frequency figure 3 shows approximate values for r set over the operating frequency range. the following equation should be used to determine r set : r = 30.2068 10 9 f 1.04414 where f is the clock frequency in hz. the resistor value determined by the equation will generate a current near center- range of the autocalibration circuit. autocalibration the ad9561 should be calibrated when power is applied to the system or after a power reduce cycle. t ac cal start cal out 1? min figure 4. autocalibration timing autocalibration is initiated by applying a pulse of 1 m s minimum duration to pin 17, cal start. the clock pulse should be applied continuously during calibration . as figure 4 shows, the initial state of cal out is not known. during the cal in pulse, all internal logic is initialized for calibration and proper synchronization once calibration is complete; the falling edge of cal in initiates the auto-cal cycle. auto-cal is not affected by the code applied to the data or control inputs. however, to assure that no pulses are generated during calibration, it is suggested that all digital inputs be held at logic 0. on the falling edge of cal in, the ramps slope is set as slow as possible for the current r set . figure 4 shows the ramp slope increasing as autocalibration adds small incremental currents, until it crosses the internal ref lo before the end of the clock period. ramp ref lo ramp end of clock cycle time figure 5. autocalibration conceptual the calibration current is incremented on each 32nd clock pulse until the full-scale ramp time is equal to the period of the clock. cal complete is detected and cal out goes high when the ramp crosses ref lo before it is reset by the next clock. with a maximum of 64 incremental increases, the maximum autocalibration time, t ac , can be calculated by the equation: t ac = 32 64 f c where: f c = clock frequency in hertz
ad9561 C6C rev. 0 this yields the maximum time from the trailing edge of cal in to the rising edge of cal out. as an example, the maximum time required for auto-calibration for a system with clock frequency of 20 mhz is 102.4 ms plus the width of the cal in pulse. power reduce the power reduce function permits the user to power down all nonessential circuits when the printer is not active. applying a logic 0 to power reduce decreases the power supply requirement by approximately half. applications data timing input data to the ad9561 is double latched. as a result of the internal timing, the output is delayed more than one clock period from its correspo nding data word. figure 6 illustrates timing of data and cont rol inputs relative to the clock. setup hold clock data control figure 6. data and control timing the data and control inputs to the ad9561 are stan- dard master-slave latches. inputs are latched in on the rising edge of the clock with 2 ns set-up time and 2 ns hold time. this is a design improvement over the ad9560 meant to simplify interfacing the ad9561 to digital processing circuits. a propagation delay exists between the clock and output pulses. the minimum propagation delay can be observed when alternating between codes 0 (00 h hexadecimal) and 255 (ff h hexadecimal). this delay is due in part to normal circuit propagation; the remainder is due to time required to imple- ment the proprietary ramp function. output pulse transi- tions will typically occur 22 ns after the rising edge of clock. it may vary from 10 nsC35 ns over temperature. transfer function output pulse width increases with increasing data values. as the heavy line of figure 7 shows, the transfer function of the ad9561 is slightly nonideal. code 100 80 0 025 pulse width ?percentage 12.5 60 40 20 128 255 figure 7. pulse width transfer function an ideal transfer would give 0% (or 0 ns) pulse width for a code 0. as the code is incremented in steps of one, the pulse width would increase by 0.39% until it reached 100% for code 255. when operating at high clock rates, several of the most narrow pulses do not reach valid logic level 1 because of finite rise time. for example, at 20 mhz, a 1.95% pulse (code 5 or 05 h ) would have an expected pulse width of 1 ns. because the rise time is typically 1.5 ns, this pulse will not reach a full output level. therefore, depending on the clock rate, the lowest set of codes produces a series of triangle waves increasing in width and ampli tude until a pulse of approximately 3 nsC5 ns reaches a proper logic level. thus, the transfer is flat until about 3 nsC5 ns pulse width (number of codes varies as a function of clock frequency). because of the new ramp topology in the ad9561, the transfer function extends slightly greater than 100% (typically 102%) of the clock period. this has the effect of creating smooth transitions at the clock period boundaries instead of the discontinuities produced by the ad9560. t pd tem (left justified) dem (center justified) lem (right justified) t clock t clock t clock t clock figure 8. dot clock period transitions as shown in figure 8, a leading edge modulated pulse followed by a trailing edge modulated pulse will stay high from the rising edge of the first pulse to the falling edge of the second. this is due to code 255 being designed to be typically 102% of the clock period. (dashed lines indicate where transitions would occur if the code for the following or preceding period were 0.) likewise, no gap occurs for maximum width trailing edge modulation to max pulse width for dual edge modula- tion. because the ending and starting characteristics of all modes are symmetrical, any combination of pulses that ends at the boundary of the first period and starts at the boundary of the second period will produce a continuous pulse across the boundary. for the purposes of printing text, or any time absolute white or black is required, 0 is decoded and a 100% low is output in the next clock cycle. similarly, 255 is detected and the next pulse is 100% high. retrace the retrace function permits driving the output to a constant logic high. for laser printer applications, applying a logic 1 to retrace holds the laser on during the retrace period so end of scan can be detected. returning it to logic low gives control back to the input data bits d0Cd7.
ad9561 C7C rev. 0 grounding and bypassing because the ad9561 uses analog circuits to achieve its superb gray scale resolution, caution must be exercised when incorpo- rating it into the mostly digital controller card for a printer. achieving the accuracy designed into the ad9561 requires that interference due to improper grounding, power supply noise and digital coupling be minimized by following good layout pr actices. it is strongly urged that all following recommendations be followed. factory characterization proves that a single ground plane dedicated to the ad9561 is most effective. this is atypical of many mixed signal circuits that use separate analog and digital grounds. due to the operating speed of the ad9561, separate grounds result in erratic performance, which is eliminated by using a single isolated ground plane. this is because the data low value can be different from the ground value of the ad9561. all pins on the ad9561 labeled ground should be connected to the single dedicated ground plane. for best results, it is suggested that this plane be in the first interior layer under the ic. to assure logic level compatibility from the drive circuits to the ad9561, a single connection to the boards main ground is necessary. the connection between the dedicated ground plane and the boards main ground should be parallel to the path of the digital signals interfacing to the ad9561. high freque ncy return current seeks the path most parallel to the signal current. whenever a parallel path does not exist, ground bounce results. clock, data and control signal traces should run from the drive logic to the ad9561 in a group parallel to the conn ection between the system ground and the ad9561 ground. using more than one signal plane will permit these traces to be as close to the ground interconnection as possible. this results in lowest impedance ground return and minimum ground interference due to digital switching. attention to subtle layout characteristics can yield significant improvement in performance of high speed mixed signal ics. the ad9561 pinouts were chosen for maximum isolation of sensitive pins such as r set . the pin 1 end of the ic should be orie nted toward the source of the high speed digital inputs. this will help assure that these signal runs are short, with essentially the same length, thus having equal propagation delays. most importantly, it will facilitate orienting traces to minimize coupling. high speed digital traces including data, clock, sem/ dem, lem/tem and the output should not pass under the body of the ic. the clock, in particular, should enter perpendicular to the ic. for best results, the output trace should exit perpendicular to the ic and pass through a via to a signal layer under the ground plane. this trace or any resistor or other component of the output circuit should not be parallel to r set as electro- magnetic coupling can occur, causing the ramp current reference to be noisy and linearity to deteriorate. optimally, r set should be a chip resistor located on the same side of the board as the ad9561. it should be located close to pin 14, without being close to the other ic pins. r set should be on the top of the board with the ad9561 with no vias to add stray reactance and additional coupling paths. to reiterate the key layout considerations, high speed digital traces should not be located near the r set pin or under the center of the ic body. a final interface consideration relates to rise/fall time of the high speed signals. some logic families have rise and fall t imes as fast as 2 v/ns. this can result in on-chip parasitic coupling of these signals into the analog section. the undesirable effect can be eliminated by inserting series resistors in the data, sem/dem and lem/ tem connections. these resistors, in conjunction with the capacitance of the input pin and bond pad, will form a low pass filter to limit slew rate of the signals. the value of these resistors should be chosen based on trading off slower rise and fall time to possible interference to set up and hold times for faster clock rates. power supply noise can also disrupt the linear circuits of the ad9561. since switching power supplies are becoming the norm in most systems, caution should be exercised to minimize switching noise reaching the ad9561. the ic is designed for maximum power supply rejection. however, frequency content of switching supply noise often exceeds the frequency range of highest rejection. the preferred method would be to use a linear regulator from a higher supply voltage. if this is not practical, insert a ferrite bead in series with the supply connection. if possible, a v dd plane or a substantial width trace should connect v dd to pin 7 first and then connect to each of the other v dd pins with wide traces. thorough decoupling will complete a low pass filter for the supply. all v dd connections should be connected together. 0.1 m f chip capacitors should be connected as closely as possible to each v dd pin to the dedicated ground plane. laboratory results indicate that performance is maximized when these chip capacitors are mounted on the same side of the pc card as the ad9561. if mounting chip components on the same side as the ad9561 is not a preferred manufacturing method, due consideration is encouraged to make an excep- tion, at least in the case of r set and as many decoupling capacitors as practical. additionally, a 10 m f tantalum capacitor should decouple the supply on the ad9561 side of the regulator or ferrite bead, also to the dedicated ground plane. for a recommended layout, see the ad9561/pcb data sheet. a copy can be obtained by calling applications support at 1-800-analogd.
ad9561 C8C rev. 0 outline dimensions dimensions shown in inches and (mm). c2938C6C12/96 printed in u.s.a. 28-lead soic (r-28) seating plane 0.0118 (0.30) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.1043 (2.65) 0.0926 (2.35) 0.0500 (1.27) bsc 0.0125 (0.32) 0.0091 (0.23) 0.0500 (1.27) 0.0157 (0.40) 8 0 0.0291 (0.74) 0.0098 (0.25) x 45 0.7125 (18.10) 0.6969 (17.70) 0.4193 (10.65) 0.3937 (10.00) 0.2992 (7.60) 0.2914 (7.40) pin 1 28 15 14 1
|
